Semiconductor memory device

ABSTRACT

A semiconductor memory device includes: a plurality of cell array blocks; a boosted voltage driving unit for selectively supplying a boosted voltage to the cell array blocks; and a controller controlling a driving operation of the boosted voltage driving unit in response to a cell array block select signal.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present invention claims priority of Korean patent applicationnumber 10-2006-0095189, filed on Sep. 28, 2006, which is incorporated byreference in its entirety.

BACKGROUND OF THE INVENTION

The present invention relates to semiconductor design technology, andmore particularly, to a power supply controller of a cell array block ina semiconductor memory device.

In general, an operational mode of a semiconductor memory device such asa dynamic random access memory (DRAM) or the like is divided into twomodes, of which one is an active mode and the other is a stand-by mode.When the semiconductor memory device is in the active mode, circuits ina chip operate to output requested data to the outside or to receiverequired data thereinto. Meanwhile, when the semiconductor memory deviceis in the stand-by mode, all current paths of circuits are cut off tominimize power consumption in the chip except for minimum number ofcircuits that are enabled to enter the active mode.

However, when the semiconductor memory device keeps in the stand-by modefor a long time, the circuits, which are enabled to enter the activemode, consume unnecessary current continuously. In particular, offleakage current mainly accounts for such an unnecessary currentconsumption in a transistor that uses a boosted voltage VPP with highvoltage level as a bias voltage.

In addition, a transistor using the boosted voltage VPP, which isapplied to an unselected cell array block in a bank even during theactive mode, as the bias voltage also generates the large amount of offleakage current undesirably as similar to the above. Herein, the cellarray block is selected by a cell array select signal generatedcorresponding to a column address. Since the boosted voltage VPP has ahigh voltage level, high electric field is applied across a source and adrain of a transistor, which causes the large amount of off leakagecurrent to be generated. Furthermore, this phenomenon of the off leakagecurrent also occurs during a self-refresh mode including a stand-bymode.

FIG. 1 is a block diagram of a conventional cell array block.

Referring to FIG. 1, the conventional cell array block includes aplurality of matrix blocks 11 having a plurality of memory cells, aplurality of sub hall regions 10, and a plurality of X-decoders 12. Thesub hall region 10 is provided with a main word line driver, a bit linesense amplifier (BLSA) driver, and a bit line isolation transistor.

The boosted voltage VPP is applied to the matrix blocks 11, the sub hallregions 10, and the X-decoders 12, respectively. Also, the boostedvoltage VPP is used as a substrate bias voltage VBB.

Here, a supply mechanism of the boosted voltage VPP will be describedbelow by using, for example, a generator for generating bit lineisolation transistor (BLIT) control signals BISHB/BISH (hereinafter,referred to as ‘BLIT control signal generator’ for simplicity) which isprovided in the sub hall region 10. Although this boosted voltage supplymechanism is also applied to transistors (drivers) using the boostedvoltage VPP as well as the BLIT control signal generator, followingillustration focuses on the BLIT control signal generator forconvenience of description.

FIG. 2 is a circuit diagram of the BLIT control signal generator.

Referring to FIG. 2, the BLIT control signal generator has an inverterstructure provided with a PMOS transistor P1 and an NMOS transistor N1.

When an input signal of a bit line isolation bar signal BISHB is at alogic low level, the PMOS transistor P1 is turned on to output a bitline isolation signal BISH by the boosted voltage VPP. The boostedvoltage VPP is also applied as the substrate bias voltage.

This is the same in both the active mode and the stand-by mode. In thesemodes, high electric field is applied across the source and the drain ofthe PMOS transistor P1, causing the large amount of off leakage currentto be generated.

That is, great amount of off leakage current is generated because theboosted voltage with high voltage level is applied to a cell array blockwhich is not selected by a cell array block select signal during theactive mode or the stand-by mode. As described above, the cell arrayblock select signal is generated by a column address signal, and selectssome of the plurality of cell array blocks.

Therefore, it is required a control circuit that can apply a voltagehaving a voltage level lower than that of the boosted voltage VPP toonly the cell array block that is not selected by the cell array blockselect signal. Here, it is noticed that an extremely low voltage cannotbe used as the voltage to be applied to the unselected cell array blockbecause the extremely low voltage must be raised to a level of theboosted voltage VPP when a corresponding cell array block is selected.That is, a response time must be delayed when using the voltageextremely lower than the boosted voltage VPP. Thus, the voltage to beapplied to the unselected cell array block must have a predeterminedvoltage level in consideration of both the off leakage current and theresponse time.

SUMMARY OF THE INVENTION

Embodiments of the present invention are directed to providing asemiconductor memory device for reducing the amount of off leakagecurrent of an unselected cell array block by applying a low voltage tothe unselected cell array block, which is smaller than a voltage appliedto a selected cell array block.

Embodiments of the present invention are also directed to providing asemiconductor memory device for reducing the amount of off leakagecurrent of an unselected cell array block by applying a low voltage tothe unselected cell array block, which is smaller than a voltage appliedto a cell array block selected during a stand-by mode or a self-refreshmode.

In accordance with the first aspect of the present invention, there isprovided a semiconductor memory device, including: a plurality of cellarray blocks; a boosted voltage driving unit for selectively supplying aboosted voltage to the cell array blocks; and a controller controlling adriving operation of the boosted voltage driving unit in response to acell array block select signal.

In accordance with the second aspect of the present invention, there isprovided a semiconductor memory device, including: a plurality of cellarray blocks; a plurality of power supply lines provided for each of thecell array blocks correspondingly; a plurality of power supply voltagedrivers provided for each of the power supply lines correspondingly tosupply a power supply voltage to the power supply lines; and a pluralityof boosted voltage drivers provided for each of the power supply linescorrespondingly to supply a boosted voltage to the power supply lines inresponse to a cell array block select signal.

In accordance with the third aspect of the present invention, there isprovided a semiconductor memory device, including: a plurality of cellarray blocks; a plurality of power supply lines provided for each of thecell array blocks correspondingly; a plurality of power supply voltagedrivers provided for each of the power supply lines correspondingly tosupply a power supply voltage to the power supply lines; and a pluralityof boosted voltage drivers provided for each of the power supply linescorrespondingly to supply a boosted voltage to the power supply lines inresponse to a cell array block select signal and a control signalindicating a stand-by mode or a self-refresh mode.

In accordance with the fourth aspect of the present invention, there isprovided a semiconductor memory device, including: a plurality of cellarray blocks; a plurality of power supply lines provided for each of thecell array blocks correspondingly; a plurality of power supply voltagedrivers provided for each of the power supply lines correspondingly tosupply a power supply voltage to the power supply lines; a plurality ofboosted voltage drivers provided for each of the power supply linescorrespondingly to supply a boosted voltage to the power supply lines;and a plurality of controllers provided for each of the boosted voltagedrivers correspondingly to control driving operations of the boostedvoltage drivers.

The present invention provides two embodiments.

In a first embodiment, a boosted voltage VPP is applied to a selectedcell array block regardless of a specific mode of a semiconductor memorydevice, whereas a power supply voltage VDD lower than the boostedvoltage VPP is applied to unselected memory cell array blocks.

In a second embodiment, the boosted voltage VPP is applied to a cellarray block selected during an active mode or a self-refresh mode,whereas the power supply voltage VDD lower than the boosted voltage VPPis applied to unselected memory cell array blocks.

Accordingly, it is possible to reduce the amount of off leakage currentin accordance with the two embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a conventional cell array block;

FIG. 2 is a circuit diagram of a bit line isolation transistor (BLIT)control signal generator;

FIG. 3 is a block diagram illustrating a power supply controller of acell array block in accordance with a first embodiment of the presentinvention;

FIG. 4 is a block diagram illustrating a power supply controller of acell array block during a stand-by mode or a self-refresh mode inaccordance with a second embodiment of the present invention; and

FIG. 5 is a circuit diagram illustrating a BLIT control signal generatoramong internal circuits of a cell array block when a power supplyvoltage is applied to the cell array block in the first and secondembodiments of FIGS. 3 and 4.

DESCRIPTION OF SPECIFIC EMBODIMENTS

Hereinafter, a semiconductor memory device in accordance with thepresent invention will be described in detail referring to theaccompanying drawings.

FIG. 3 is a block diagram illustrating a power supply controller of acell array block in accordance with a first embodiment of the presentinvention.

Referring to FIG. 3, the power supply controller of the cell array blockincludes a plurality of cell array blocks 101 to 106, a plurality ofpower supply lines corresponding to the plurality of cell array blocks101 to 106, a plurality of boosted voltage driving units 201 to 206, anda controller.

The power supply lines are disposed between the cell array blocks 101 to106 and the boosted voltage driving units 201 to 206. Each of theboosted voltage driving units 201 to 206 supplies a boosted voltage VPPto the cell array blocks 101 to 106, respectively. The controller 113controls driving operations of the boosted voltage driving units 201 to206 in response to first to fifth cell array block select signals MS0Bto MS4B.

Herein, each of the plurality of boosted voltage driving units 201 to206 includes a clamping circuit for supplying a clamped voltage, whichis lower than the boosted voltage VPP, to unselected cell array blocks101 to 106 in response to the first to fifth cell array block selectsignals MS0B to MS4B. Each of the plurality of boosted voltage drivingunits 201 to 206 includes a voltage down converter for lowering theboosted voltage VPP to apply the lowered voltage to the unselected cellarray blocks 101 to 106 in response to the first to fifth cell arrayblock select signals MS0B to MS4B.

The clamping circuit and the voltage down converter, which correspond toreference numerals 107A to 112A, are provided in the boosted voltagedriving unit so as to apply the voltage lower than the boosted voltageVPP to the unselected cell array blocks 101 to 106.

In more detail, the plurality of boosted voltage driving units 201 to206 include a plurality of power supply voltage drivers 107A to 112Acorresponding to the power supply lines to supply a power supply voltageVDD to the power supply lines, and a plurality of boosted voltagedrivers 107B to 112B corresponding to the power supply lines to supplythe boosted voltage VPP to the power supply lines.

Each of the cell array blocks 101 to 106 includes a matrix block havinga memory cell singly or in plurality, a sub hall region and anX-decoder. The sub hall region is provided with a main word driver, abit line sense amplifier (BLSA) driver, a bit line isolation transistor(BLIT) control signal generator, and the like.

The cell array blocks 101 to 106 use the boosted voltage VPP as asubstrate bias voltage, and thus these are regions where the boostedvoltage VPP is much consumed generally.

The sub hall region has an effect on adjacent matrix blocks in general.For example, the second sub hall region has an effect on both the firstand second matrix blocks but it is shown that one matrix block and onesub hall region are provided in each of the cell array blocks 101 to 106for convenience of description in the embodiment.

The BLIT control signal generator provided in the sub hall regionreceives a source power through the boosted voltage driving units 201 to206. The boosted voltage VPP is applied to a well of the BLIT controlsignal generator without passing through the boosted voltage drivingunits 201 to 206.

The controller 113 includes first to sixth control signal generatingcircuits 114 to 119 corresponding to the plurality of booted voltagedrivers 107B to 112B to control driving operations of the boostedvoltage drivers 107B to 112B. In detail, the controller 113 includes thefirst control signal generating circuit 114 for generating a firstcontrol signal CONSIG0 to drive the first boosted voltage driver 107B inresponse to the first cell array select signal MS0B, the second controlsignal generating circuit 115 for generating a second control signalCONSIG1 to drive the second boosted voltage driver 108B in response tothe first and second cell array select signals MS0B and MS1B, the thirdcontrol signal generating circuit 116 for generating a third controlsignal CONSIG2 to drive the third boosted voltage driver 109B inresponse to the second and third cell array select signals MS1B andMS2B, the fourth control signal generating circuit 117 for generating afourth control signal CONSIG3 to drive the fourth boosted voltage driver110B in response to the third and fourth cell array select signals MS2Band MS3B, the fifth control signal generating circuit 118 for generatinga fifth control signal CONSIG4 to drive the fifth boosted voltage driver111B in response to the fourth and fifth cell array select signals MS3Band MS4B, and the sixth control signal generating circuit 119 forgenerating a sixth control signal CONSIG5 to drive the sixth boostedvoltage driver 112B in response to the fifth cell array select signalMS4B.

In more detail, the first control signal generating circuit 114 includesfirst and second inverters INV1 and INV2 and a first level shifter L/S1.The first and second inverters INV1 and INV2 buffer the first cell arrayselect signal MS0B. The first level shifter L/S1 shifts a level of anoutput signal of the second inverter INV2 to output the shifted signalas the first control signal CONSIG0.

The second control signal generating circuit 115 is provided with afirst NAND gate NAND1, a third inverter INV3 and a second level shifterL/S2. The first NAND gate NAND1 performs a NAND operation on the firstand second cell array select signals MS0B and MS1B. The third inverterINV3 inverts an output signal of the first NAND gate NAND1. The secondlevel shifter L/S2 shifts a level of an output signal of the thirdinverter INV3 to output the shifted signal as the second control signalCONSIG1.

The third control signal generating circuit 116 is provided with asecond NAND gate NAND2, a fourth inverter INV4 and a third level shifterL/S3. The second NAND gate NAND2 performs a NAND operation on the secondand third cell array select signals MS1B and MS2B. The fourth inverterINV4 inverts an output signal of the second NAND gate NAND2. The thirdlevel shifter L/S3 shifts a level of an output signal of the fourthinverter INV4 to output the shifted signal as the third control signalCONSIG2.

The fourth control signal generating circuit 117 is provided with athird NAND gate NAND3, a fifth inverter INV5 and a fourth level shifterL/S4. The third NAND gate NAND3 performs a NAND operation on the thirdand fourth cell array select signals MS2B and MS3B. The fifth inverterINV5 inverts an output signal of the third NAND gate NAND3. The fourthlevel shifter L/S4 shifts a level of an output signal of the fifthinverter INV5 to output the shifted signal as the fourth control signalCONSIG3.

The fifth control signal generating circuit 118 is provided with afourth NAND gate NAND4, a sixth inverter INV6 and a fifth level shifterL/S5. The fourth NAND gate NAND4 performs NAND operation on the fourthand fifth cell array select signals MS3B and MS4B. The sixth inverterINV6 inverts an output signal of the fourth NAND gate NAND4. The fifthlevel shifter L/S5 shifts a level of an output signal of the sixthinverter INV6 to output the shifted signal as the fifth control signalCONSIG4.

The sixth control signal generating circuit 119 is provided with seventhand eighth inverters INV7 and INV8 for buffering the fifth cell arrayselect signal MS4B, and a sixth level shifter L/S6 for shifting a levelof an output signal of the eighth inverter INV8 to output the shiftedsignal as the sixth control signal CONSIG5.

The first to sixth control signals CONSIG0 to CONSIG5 are generated asabove to acquire logic levels corresponding to the logic levels of thecell array block select signals MS0B to MS4B, and thus the first tosixth boosted voltage drivers 107B to 112B operate.

The second through fifth control signal generating circuits 115 to 118use two cell array select signals because the sub hall region isdisposed between adjacent two matrix blocks to control operations of thetwo adjacent matrix blocks.

The first to sixth boosted voltage drivers 107B to 112B are circuits fordriving main circuits in the cell array blocks 101 to 106 by applyingthe boosted voltage VPP to the selected cell array blocks 101 to 106. Tothis end, the boosted voltage drivers 107B to 112B are configured withPMOS transistors P2 to P7 using the first to sixth control signalsCONSIG0 to CONSIG5 outputted from the controller 113 as gate inputsignals, of which sources are connected to a boosted voltage terminaland drains are connected to the power supply line.

The boosted voltage VPP is used as a bias voltage of a substrate wherethe cell array blocks 101 to 106 are provided.

Thereafter, the power supply voltage drivers 107A to 112A apply thepower supply voltage VDD to unselected cell array blocks 101 to 106.

To this end, the power supply voltage drivers 107A to 112A areconfigured with NMOS transistors N2 to N7 of which sources and gates arecommonly connected to a power supply terminal, and drains are connectedto the power supply line.

An operation of the power supply controller of the cell array blocks 101to 106 will be described below. For convenience of description, it isassumed that the first and second cell array blocks 101 and 102 areselected by the first to fifth cell array block select signals MS0B toMS4B, and the other cell array blocks 103 to 106 are not selected.

The first and second control signals CONSIG0 and CONSIG1 of the firstand second control signal generating circuits 114 and 115 become a logiclow level in response to first and second cell array block selectsignals MS0B to MS1B so that the first and second boosted voltagedrivers 107B and 108B operate. Accordingly, the boosted voltage VPP isapplied to the first and second cell array blocks 101 and 102, therebyoperating various kinds of circuits, e.g., circuits using the boostedvoltage VPP as a driving voltage, provided in the corresponding cellarray blocks 101 and 102.

Meanwhile, the third to sixth control signals CONSIG2 to CONSIG5 of thethird to sixth control signal generating circuits 116 to 119 become alogic high level by the third to fifth cell array block select signalsMS2B to MS4B so that the corresponding boosted voltage drivers 109B to112B do not operate. Therefore, the output voltages of the power supplyvoltage drivers 109A to 112A are applied to the corresponding cell arrayblocks 103 to 106. At this point, since the corresponding cell arrayblocks 103 to 106 operate in the same manner as the stand-by mode, theydo not erroneously operate even if a voltage, e.g., the power supplyvoltage, lower than the boosted voltage VPP is applied.

In summary, the boosted voltage VPP is applied to the selected cellarray blocks 101 and 102, whereas the power supply voltage VDD isapplied to the unselected cell array blocks 103 to 106. This makes itpossible to reduce the amount of off leakage current in the inventivepower supply controller applying the power supply voltage VDD to theunselected cell array blocks 103 to 106, compared to the prior art casewhere the boosted voltage VPP is applied to the unselected cell arrayblocks 103 to 106.

In the embodiment as described above, the power supply control method ofthe cell array block has been illustrated regardless of a specificoperation mode of a semiconductor memory device. Specifically, the powersupply control method of the cell array block during a stand-by modewill be described below.

FIG. 4 is a block diagram illustrating a power supply controller of acell array block during a stand-by mode or a self-refresh mode inaccordance with a second embodiment of the present invention.

Referring to FIG. 4, during the stand-by mode or the self-refresh mode,the power supply controller of the cell array block in accordance withthe second embodiment includes a plurality of cell array blocks 151 to156, a plurality of boosted voltage driving units 250 to 255 supplying aboosted voltage VPP to the plurality of cell array blocks 151 to 156,and a controller 163 controlling driving operations of the boostedvoltage driving units 250 to 255 in response to first to fifth cellarray block select signals MS0B to MS4B and a power down mode signalPWDDB. Hereinafter, the power down mode signal PWDDB, which controls theself-refresh mode or the stand-by mode, will indicate the stand-by modebut it is noted that it includes the self-refresh mode.

Here, each of the plurality of boosted voltage driving units 250 to 255includes a clamping circuit for providing a clamped voltage, which islower than the boosted voltage VPP, to unselected cell array blocks 151to 156 in response to the cell array block select signals MS0B to MS4B.Each of the plurality of boosted voltage driving units 250 to 255includes a voltage down converter for lowering the boosted voltage VPPto apply the lowered voltage to the unselected cell array blocks 151 to156 in response to the first to fifth cell array block select signalsMS0B to MS4B during the stand-by mode or the self-refresh mode.

The clamping circuit and the voltage down converter, which correspond toreference numerals 157A to 162A of FIG. 4, are provided in the boostedvoltage driving unit so as to apply the voltage lower than the boostedvoltage VPP to the unselected cell array blocks 151 to 156.

In more detail, the power supply controller in accordance with theanother embodiment of the present invention includes the plurality ofcell array blocks 151 to 156, a plurality of power supply linescorresponding to the plurality of cell array blocks 151 to 156, aplurality of power supply voltage drivers 157A to 162A corresponding tothe power supply lines to supply a power supply voltage VDD to the powersupply lines, a plurality of boosted voltage drivers 157B to 162Bcorresponding to the power supply lines to supply the boosted voltageVPP to the power supply lines, and a plurality of controllers 164 to 169corresponding to the plurality of booted voltage drivers 157B to 162B tocontrol driving operations of the boosted voltage drivers 157B to 162B.Herein, each of the power supply voltage drivers 157A to 162A and eachof the boosted voltage drivers 157B to 162B are included in thecorresponding boosted voltage driving unit 250 to 255. The plurality ofpower supply lines are disposed between the cell array blocks 151 to 156and the boosted voltage driving units 250 to 255.

Each of the cell array blocks 151 to 156 includes a matrix block havinga memory cell singly or in a plurality, a sub hall region and anX-decoder. The sub hall region is provided with a main word driver, aBLSA driver, a BLIT control signal generator, and the like.

The cell array blocks 151 to 156 use the boosted voltage VPP as asubstrate bias voltage, and thus these are regions where the boostedvoltage VPP is much consumed generally.

The sub hall region has an effect on adjacent matrix blocks in general.For example, the second sub hall region has an effect on both the firstand second matrix blocks but it is shown that one matrix block and onesub hall region are provided in each of the cell array blocks 151 to 156in the embodiment for convenience of description.

The BLIT control signal generator provided in the sub hall regionreceives a source power through the boosted voltage driving units 250 to255. The boosted voltage VPP is applied to a well of the BLIT controlsignal generator without passing through the boosted voltage drivingunits 250 to 255.

The controller 163 applies the power supply voltage VDD having lowervoltage level than the boosted voltage VPP to the cell array blocks 151to 156 when a memory device enters the stand-by mode or the self-refreshmode. The controller 163 includes a first control signal generatingcircuit 164 for generating a first control signal CONSIG0 to drive afirst boosted voltage driver 157B in response to the first cell arrayselect signal MS0B and the power down mode signal PWDDB, a secondcontrol signal generating circuit 165 for generating a second controlsignal CONSIG1 to drive a second boosted voltage driver 158B in responseto the first and second cell array select signals MS0B and MS1B and thepower down mode signal PWDDB, a third control signal generating circuit166 for generating a third control signal CONSIG2 to drive a thirdboosted voltage driver 159B in response to the second and third cellarray select signals MS1B and MS2B and the power down mode signal PWDDB,a fourth control signal generating circuit 167 for generating a fourthcontrol signal CONSIG3 to drive a fourth boosted voltage driver 160B inresponse to the third and fourth cell array select signals MS2B and MS3Band the power down mode signal PWDDB, a fifth control signal generatingcircuit 168 for generating a fifth control signal CONSIG4 to drive afifth boosted voltage driver 161B in response to the fourth and fifthcell array select signals MS3B and MS4B and the power down mode signalPWDDB, and a sixth control signal generating circuit 169 for generatinga sixth control signal CONSIG5 to drive a sixth boosted voltage driver162B in response to the fifth cell array select signal MS4B and thepower down mode signal PWDDB.

In more detail, the first control signal generating circuit 164 isprovided with a first inverter INV9 for inverting the first cell arrayselect signal MS0B, a first NOR gate NOR1 for performing a NOR operationon an output signal of the first inverter INV9 and the power down modesignal PWDDB, and a first level shifter L/S11 for shifting a level of anoutput signal of the first NOR gate NOR1 to output the shifted signal asthe first control signal CONSIG0.

The second control signal generating circuit 165 is provided with afirst NAND gate NAND5 for performing a NAND operation on the first andsecond cell array select signals MS0B and MS1B, a second NOR gate NOR2for performing a NOR operation on an output signal of the first NANDgate NAND5 and the power down mode signal PWDDB, and a second levelshifter L/S12 for shifting a level of an output signal of the second NORgate NOR2 to output the shifted signal as the second control signalCONSIG1.

The third control signal generating circuit 166 is provided with asecond NAND gate NAND6 for performing a NAND operation on the second andthird cell array select signals MS1B and MS2B, a third NOR gate NOR3 forperforming a NOR operation on an output signal of the second NAND gateNAND6 and the power down mode signal PWDDB, and a third level shifterL/S13 for shifting a level of an output signal of the NOR gate NOR3 tooutput the shifted signal as the third control signal CONSIG2.

The fourth control signal generating circuit 167 is provided with athird NAND gate NAND7 for performing a NAND operation on the third andfourth cell array select signals MS2B and MS3B, a fourth NOR gate NOR4for performing a NOR operation on an output signal of the third NANDgate NAND7 and the power down mode signal PWDDB, and a fourth levelshifter L/S14 for shifting a level of an output signal of the fourth NORgate NOR4 to output the shifted signal as the fourth control signalCONSIG3.

The fifth control signal generating circuit 168 is provided with afourth NAND gate NAND8 for performing a NAND operation on the fourth andfifth cell array select signals MS3B and MS4B, a fifth NOR gate NOR5 forperforming a NOR operation ono an output signal of the fourth NAND gateNAND8 and the power down mode signal PWDDB, and a fifth level shifterL/S15 for shifting a level of an output signal of the fifth NOR gateNOR5 to output the shifted signal as the fifth control signal CONSIG4.

The sixth control signal generating circuit 169 is provided with asecond inverter INV10 for inverting the fifth cell array select signalMS4B, a sixth NOR gate NOR6 for performing a NOR operation on an outputsignal of the second inverter INV10 and the power down mode signalPWDDB, and a sixth level shifter L/S16 for shifting a level of an outputsignal of the sixth NOR gate NOR6 to output the shifted signal as thesixth control signal CONSIG5.

The first to sixth control signals CONSIG0 to CONSIG5 are generated asabove to acquire logic levels corresponding to the logic levels of thepower down mode signal PWDDB and the cell array block select signalsMS0B to MS4B, and thus the boosted voltage drivers 157B to 162B operate.

The second to fifth control signal generating circuits 165 to 168 usetwo cell array select signals because the sub hall region is disposedbetween adjacent two matrix blocks to control operations of the twoadjacent matrix blocks.

The boosted voltage drivers 157B to 162B are circuits for driving maincircuits in the cell array blocks 151 to 156 by applying the boostedvoltage VPP to the selected cell array blocks 151 to 156. To this end,the boosted voltage drivers 157B to 162B are configured with PMOStransistors P8 to P13 using the first to sixth control signals CONSIG0to CONSIG5 outputted from the controller 163 as gate input signals, ofwhich sources are connected to the boosted voltage terminal and drainsare connected to the power supply line.

The boosted voltage VPP is used as a bias voltage of a substrate wherethe cell array blocks 151 to 156 are provided.

Thereafter, the power supply voltage drivers 157A to 162A apply thepower supply voltage VDD to unselected cell array blocks 151 to 156.

To this end, the power supply voltage drivers 157A to 162A areconfigured with NMOS transistors N8 to N13 of which sources and gatesare commonly connected to a power supply terminal, and drains areconnected to the power supply line.

An operation of the power supply controller of the cell array block 151to 156 may be mainly divided into two modes, of which one is an activemode and the other is a stand-by mode including a self-refresh mode.

That is, levels of voltages applied to the cell array blocks 151 to 156primarily change depending on a logic level of the power down modesignal PWDDB. Afterwards, the levels of the voltages applied to the cellarray blocks 151 to 156 secondarily change in response to the cell arrayblock select signals MS0B to MS4B. Such an operation is determined bythe first to sixth control signals CONSIG0 to CONSIG5 of the controller163.

For example, when a semiconductor memory device enters the active mode,the power down mode signal PWDDB becomes a logic high level.Accordingly, the first to sixth control signals CONSIG0 to CONSIG5 ofthe controller 163 become a logic low level to apply the boosted voltageVPP to the cell array blocks 151 to 156.

That is, when the semiconductor memory device is in the active mode, theboosted voltage VPP is applied to all cell array blocks 151 to 156regardless of selection or unselection of the cell array blocks 151 to156 by the cell array block select signals MS0B to MS4B.

Alternatively, when the semiconductor memory device enters the stand-bymode or the self-refresh mode, the power down mode signal PWDDB becomesa logic low level. Only the first cell array block select signal MS0Bbecomes a logic low level to select the first cell array block 151.

In response to the power down mode signal PWDDB and the first cell arrayblock select signal MS0B, only the first control signal CONSIG0 becomesa logic low level, and other control signals CONSIG1 to CONSIG5 become alogic high level.

Therefore, the boosted voltage VPP is applied to only the selected firstcell array block 151, whereas the power supply voltage VDD lower thanthe boosted voltage VPP is applied to the other cell array blocks 152 to156 which are not selected.

That is, in this case, the boosted voltage VPP is applied to the wholecell array blocks 151 to 156 during the active mode. During the stand-bymode or the self-refresh mode, the boosted voltage VPP is applied to thecell array block 151 selected by the cell array block select signalMS0B, whereas the power supply voltage VDD is applied to the unselectedcell array blocks 152 to 156.

FIG. 5 is a circuit diagram illustrating a BLIT control signal generatoramong internal circuits of a cell array block when the power supplyvoltage VDD is applied to the cell array blocks in the embodiments ofFIGS. 3 and 4. Here, the BLIT control signal generator, which operatesusing the boosted voltage as a driving voltage, is a representativecircuit among various circuits using the boosted voltage VPP as thedriving voltage in the cell array block.

Referring to FIG. 5, the BLIT control signal generator has an inverterstructure provided with a PMOS transistor P14 and an NMOS transistorN14, as illustrated in FIG. 2.

In the conventional BLIT control signal generator of FIG. 2, the boostedvoltage VPP is used as the substrate bias voltage even during thestand-by mode, the self-refresh mode, and a mode when the cell arrayblocks are not selected by the cell array block signal, and the boostedvoltage VPP is also applied to a source of the PMOS transistor P14.

However, in the present invention, the boosted voltage VPP is used asthe substrate bias voltage during the stand-by mode, the self-refreshmode, and a mode when the cell array blocks are not selected by the cellarray block signal, whereas the power supply voltage VDD is applied tothe source of the PMOS transistor P14.

In the present invention, the substrate bias voltage, i.e., the boostedvoltage VPP, and the power supply voltage VDD are separately used forsecuring sufficient time when the memory device enters active mode fromthe stand-by mode, the self-refresh mode and the mode when the cellarray blocks are not selected by the cell array block select signals,because the well has large capacitance.

In summary, the two embodiments of the present invention are describedabove for reducing off leakage current.

First, the selected cell array blocks and the unselected cell arrayblocks are divided regardless of a specific operational mode of thesemiconductor memory device. In this case, the boosted voltage VPP,which is a driving voltage required for operation, is applied to theselected cell array blocks, whereas the power supply voltage VDD lowerthan the boosted voltage VPP is applied to the unselected memory cellarray blocks to reduce the amount of off leakage current.

Second, the operation mode is divided into the active mode and thestand-by mode (or self-refresh mode), and the boosted voltage VPP isapplied to all the cell array blocks during the active mode. However,during the stand-by mode (or self-refresh mode), the boosted voltage VPPis only applied to the selected cell array blocks, whereas the powersupply voltage VDD lower than the boosted voltage VPP is applied to theunselected memory cell array blocks to reduce the amount of off leakagecurrent.

Therefore, in comparison with the prior art case where the boostedvoltage having high voltage level is applied to the cell array blockswhich do not operate, the semiconductive memory device of the presentinvention can reduce the amount of off leakage current by applying thepower supply voltage which is lower than the boosted voltage.

As described above, the present invention can reduce the amount of offleakage current caused by the boosted voltage VPP in a semiconductormemory device.

Accordingly, it is possible to reduce the amount of power consumption inthe semiconductor memory device, which increases fabrication yield ofthe semiconductor memory device.

While the present invention has been described with respect to thespecific embodiments, it will be apparent to those skilled in the artthat various changes and modifications may be made without departingfrom the spirit and scope of the invention as defined in the followingclaims.

For example, kinds and configurations of logics used in theaforementioned embodiments have been exemplarily illustrated assumingthat all input and output signals are activated at logic high levels.Therefore, the logics may be differently modified in case whereactivation polarities of the signals are changed. However, since suchmodified embodiments are too numerous and they can be easily deducedfrom the aforementioned embodiments of the present invention by thoseskilled in the art, direct description of them will be omitted herein.

1. A semiconductor memory device, comprising: a plurality of cell arrayblocks; a boosted voltage driving unit for selectively supplying aboosted voltage to the cell array blocks; and a controller controlling adriving operation of the boosted voltage driving unit in response to acell array block select signal.
 2. The semiconductor memory device asrecited in claim 1, wherein the controller drives the boosted voltagedriving unit in response to a control signal indicating a stand-by modeor a self-refresh mode.
 3. The semiconductor memory device as recited inclaim 1, wherein the boosted voltage driving unit supplies the boostedvoltage to only a selected cell array block in response to the cellarray block select signal.
 4. The semiconductor memory device as recitedin claim 2, wherein the boosted voltage driving unit supplies theboosted voltage to all of the cell array blocks during an active modeand supplies the boosted voltage to only a selected cell array blockduring the stand-by mode or the self-refresh mode in response to thecell array block select signal and the control signal.
 5. Thesemiconductor memory device as recited in claim 1, wherein the cellarray block comprises a bit line isolation transistor (BLIT) controlsignal generator, the BLIT control signal generator receiving a sourcepower through the boosted voltage driving unit, and the boosted voltagebeing applied to a well of the BLIT control signal generator withoutpassing through the boosted voltage driving unit.
 6. The semiconductormemory device as recited in claim 1, wherein the boosted voltage drivingunit comprises a clamping circuit for supplying a clamped voltage lowerthan the boosted voltage to an unselected cell array block in responseto the cell array block select signal.
 7. The semiconductor memorydevice as recited in claim 1, wherein the boosted voltage driving unitcomprises a voltage down converter for lowering the boosted voltage tosupply the lowered voltage to an unselected cell array block in responseto the cell array block select signal.
 8. The semiconductor memorydevice as recited in claim 1, wherein the boosted voltage driving unitcomprises: a power supply line connected to the cell array block; apower supply voltage driver for supplying a power supply voltage to thepower supply line; and a boosted voltage driver for supplying theboosted voltage to the power supply line under control of thecontroller.
 9. The semiconductor memory device as recited in claim 8,wherein the power supply voltage driver comprises an n-type metal oxidesemiconductor (NMOS) transistor of which a source and a gate arecommonly connected to a power supply terminal and a drain is connectedto the power supply line.
 10. The semiconductor memory device as recitedin claim 8, wherein the boosted voltage driver comprises a p-type metaloxide semiconductor (PMOS) transistor of which a source is connected toa boosted voltage terminal, a drain is connected to a power supply line,and a gate receives an output signal of the controller.
 11. Asemiconductor memory device, comprising: a plurality of cell arrayblocks; a plurality of power supply lines provided for each of the cellarray blocks correspondingly; a plurality of power supply voltagedrivers provided for each of the power supply lines correspondingly tosupply a power supply voltage to the power supply lines; and a pluralityof boosted voltage drivers provided for each of the power supply linescorrespondingly to supply a boosted voltage to the power supply lines inresponse to a cell array block select signal.
 12. The semiconductormemory device as recited in claim 11, wherein the cell array blockcomprises a bit line isolation transistor (BLIT) control signalgenerator, the boosted voltage being applied to the BLIT control signalgenerator without passing through the boosted voltage driver.
 13. Thesemiconductor memory device as recited in claim 11, wherein the cellarray block comprises a BLIT control signal generator, the BLIT controlsignal generator receiving a source power through the boosted voltagedriver, and the boosted voltage being applied to a well of the BLITcontrol signal generator without passing through the boosted voltagedriver.
 14. The semiconductor memory device as recited in claim 11,wherein the boosted voltage driver comprises a PMOS transistor of whicha source is connected to a boosted voltage terminal, a drain isconnected to the power supply line, and a gate receives a controlsignal.
 15. A semiconductor memory device, comprising: a plurality ofcell array blocks; a plurality of power supply lines provided for eachof the cell array blocks correspondingly; a plurality of power supplyvoltage drivers provided for each of the power supply linescorrespondingly to supply a power supply voltage to the power supplylines; and a plurality of boosted voltage drivers provided for each ofthe power supply lines correspondingly to supply a boosted voltage tothe power supply lines in response to a cell array block select signaland a control signal indicating a stand-by mode or a self-refresh mode.16. The semiconductor memory device as recited in claim 15, wherein thecell array block comprises a bit line isolation transistor (BLIT)control signal generator, the boosted voltage being applied to the BLITcontrol signal generator without passing through the boosted voltagedriver.
 17. The semiconductor memory device as recited in claim 15,wherein the cell array block comprises a BLIT control signal generator,the BLIT control signal generator receiving a source power through theboosted voltage driver, and the boosted voltage being applied to a wellof the BLIT control signal generator without passing through the boostedvoltage driver.
 18. The semiconductor memory device as recited in claim15, wherein the boosted voltage driver comprises a PMOS transistor ofwhich a source is connected to a boosted voltage terminal, a drain isconnected to the power supply line, and a gate receives the controlsignal.
 19. A semiconductor memory device, comprising: a plurality ofcell array blocks; a plurality of power supply lines provided for eachof the cell array blocks correspondingly; a plurality of power supplyvoltage drivers provided for each of the power supply linescorrespondingly to supply a power supply voltage to the power supplylines; a plurality of boosted voltage drivers provided for each of thepower supply lines correspondingly to supply a boosted voltage to thepower supply lines; and a plurality of controllers provided for each ofthe boosted voltage drivers correspondingly to control drivingoperations of the boosted voltage drivers.
 20. The semiconductor memorydevice as recited in claim 19, wherein the controller drives the boostedvoltage driver in response to a control signal indicating a stand-bymode or a self-refresh mode.
 21. The semiconductor memory device asrecited in claim 20, wherein the boosted voltage driver supplies theboosted voltage to only a selected cell array block in response to acell array block select signal.
 22. The semiconductor memory device asrecited in claim 21, wherein the boosted voltage driver supplies theboosted voltage to all of the cell array blocks during an active modeand supplies the boosted voltage to only a selected cell array blockduring the stand-by mode or the self-refresh mode in response to thecell array block select signal and the control signal.
 23. Thesemiconductor memory device as recited in claim 19, wherein the cellarray block comprises a bit line isolation transistor (BLIT) controlsignal generator, the boosted voltage being applied to the BLIT controlsignal generator without passing through the boosted voltage driver. 24.The semiconductor memory device as recited in claim 19, wherein the cellarray block comprises a BLIT control signal generator, the BLIT controlsignal generator receiving a source power through the boosted voltagedriver, and the boosted voltage being applied to a well of the BLITcontrol signal generator without passing through the boosted voltagedriver.
 25. The semiconductor memory device as recited in claim 19,wherein the boosted voltage driver comprises a PMOS transistor of whicha source is connected to a boosted voltage terminal, a drain isconnected to the power supply line, and a gate receives an output signalof the controller.